Without limiting the scope of the invention, its background is described in connection with the manufacture and formation of CMOS integrated circuit components for dual voltages, as an example.
Heretofore in this field, to improve reliability and reduce power consumption, the supply voltage of CMOS devices has been diminished with decreasing feature sizes and increasing performance. While circuit voltages are approaching 1 V, however, external supply voltages may remain at higher values from 1.5 to 5 V. This calls for mixed voltage CMOS technologies where the core circuits typically utilize very low voltages, such as a voltage between approximately 1.5 V to 1.8 V, and the input-output circuits typically use higher supply voltages, such as a voltage between approximately 3.3 V to 5 V.
The merger of low and high voltages becomes increasingly difficult to accomplish without an increase in the number of lithography steps. At the same time, the well known hot electron problems in the NMOS transistors at high drain voltages are of serious concern.
Various approaches have been aimed at reducing the voltage stress at the drains of N-transistors or reducing the intensity of electric fields in the channel region to minimize the generation of hot electrons, such as a normal lightly doped drain (LDD). A common approach to fabricating devices on the same substrate with different operating voltages is to reproduce existing process flows for low voltage and high voltage circuits separately. The result is differentiated gate length, gate oxide thickness, source-drain extensions and junctions, as shown in FIG. 1. Thus, the low voltage circuits have short channel lengths, thin gate oxides, shallow source-drain extensions, and shallow source-drain areas, while the high voltage circuits have longer channel lengths, thicker gate oxides, deeper source-drain extensions, and deeper source-drain areas. This is, however, a very expensive and time consuming approach.
An alternative is to incorporate in high voltage circuits source-drain extensions and junctions that are suitable for low voltage circuits, as depicted in FIG. 2. As shown in FIG. 2, the high voltage circuit has a longer channel length and thicker gate oxide than the low voltage circuit, but both have shallow source-drain areas and shallow source-drain extensions. In this case, the high voltage circuits would therefore have poor hot carrier reliability because of the high electric fields under the gate oxide by the junction. Electrostatic discharge protection may also be lacking because of the shallow junctions.
Deepening the junctions to alleviate this problem by increasing the implant energy, as shown in FIG. 3, degrades the performance of low voltage transistors because of increased junction capacitance and lower current drive. As shown in FIG. 3, the high voltage circuits have longer channel lengths and thicker gate oxides than the low voltage circuits, while both have intermediate source-drain areas and intermediate source-drain extensions. Thus, the dilemma between product reliability and economical efficiency calls for a process improvement to resolve these two conflicting factors.